樋上 喜信　教授

HIGAMI Yoshinobu

略歴

  • 1996年　大阪大学大学院工学研究科応用物理専攻博士後期課程了
  • 1996年　日本学術振興会特別研究員採用
  • 1997年　ウィスコンシン大学客員研究員
  • 1998年　愛媛大学工学部助手
  • 2006年　ウィスコンシン大学客員研究員
  • 現在　　 愛媛大学大学院理工学研究科教授

受賞歴

  1. 平成16年度電子情報通信学会論文賞
  2. 平成23年度電子情報通信学会論文賞
  3. Best Paper Award, IEEE Computer Society Annual Symposium on VLSI 2014
  4. 日本信頼性学会2015年度高木賞

研究テーマ

LSIの故障検査および組み込みシステムの設計とテスト

  1. LSIのテストパターン生成の故障診断
  2. LSI設計ツール開発
  3. 組み込みシステムの自動テスト生成
  4. 組み込みシステムのハード／ソフト協調テスト

研究業績 (研究者ポータルサイト (researchmap) にも掲載)

著書

  1. LSIテスティング学会編 (編集委員長 中前幸治), "LSIテスティングハンドブック", オーム社, 2008年.
  2. K. Kondo, M. Kada, and K. Takahashi ed.: "Three-Dimensional Integration of Semiconductors," Chapter 8, Sections 3, 4, Springer, 2015.

学位論文

  • 論文題名「順序回路に対する短縮スキャンシフト法とテスト系列生成法に関する研究」 大阪大学大学院理工学研究科
    学位 博士(工学)
    1996年3月取得

論文誌

  1. Y. Higami, S. Kajihara, and K. Kinoshita, "Test Sequence Generation for Sequential Circuits Using Distinguishing Sequences," IEICE Transactions on Fundamentals, Vol. E76-A, No. 10, 1730-1737, Oct. 1993.
  2. Y. Higami, S. Kajihara, and K. Kinoshita, "A Reduced Scan Shift Method for Sequential Circuit Testing," IEICE Transactions on Fundamentals, Vol. E77-A, No. 12, pp. 2010-2016, Dec. 1994.
  3. Y. Higami, S. Kajihara, and K. Kinoshita, "Partial Scan Design and Test Sequence Generation Based on Reduced Scan Shift Method," Journal of Electronic Testing Theory and Applications, Vol. 7, No. 1/2, pp. 115-124, Aug./Oct. 1995.
  4. T. Maeda, Y. Higami and K. Kinoshita, "Test Generation for Sequential Circuits under IDDQ Testing," IEICE Transactions on Information and Systems, Vol. E81-D, No. 7, pp. 689-696, July 1998.
  5. 樋上喜信, K.K.Saluja, 高松雄三, 樹下行三, ”順序回路のブリッジ故障に対する IDDQ テストのための静的なテスト系列圧縮法,” 電子情報通信学会論文誌, Vol. J82-D-I, No. 7, pp. 879-887, 1999年7月.
  6. Y. Higami, K. K. Saluja, Y. Takamatsu and K. Kinoshita, “Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits,” Journal of Electronic Testing Theory and Applications, Vol. 16, No. 5, pp. 443-452, Oct. 2000.
  7. Y. Higami, K. K. Saluja, Y. Takamatsu and K. Kinoshita, “Static Test Compaction for IDDQ Testing of Bridging Faults in Sequential Circuits,” Systems and Computers in Japan, Vol. 31, No. 11, pp.41-50, Nov. 2000.
  8. 樋上喜信, 高松雄三, 樹下行三, ”リセット機能を持つ順序回路に対するテスト系列圧縮法,” 情報処理学会論文誌, Vol. 42, No. 4, pp. 1036-1044, 2001年4月.
  9. 樋上喜信, 小林真也, 高松雄三, “順序回路に対する消費電力削減のためのテストベ クトル変更法,” 情報処理学会論文誌, Vol. 43, No. 5, pp. 1269-1277, 2002年5月.
  10. H. Takahashi, M. Phadoongsidhi, Y. Higami, K. K. Saluja and Y. Takamatsu, “Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation,” IEICE Transactions on Information and Systems, Vol. E85-D, No. 10, pp. 1515-1525, Oct. 2002.
  11. 樋上喜信, 梶原誠司, 市原英行, 高松雄三, “[サーベイ論文]論理回路に対するテストコスト削減法 - テストデータ量およびテスト実行時間の削減-”, 電子情報通信 学会論文誌 D-I, Vol. J87-D-I, No. 3, pp.291-307, 2004年3月. (平成16年度 論文賞受賞)
  12. Y. Higami, S. Kobayashi and Y. Takamatsu, “Generation of Test Sequences with Low Power Dissipation for Sequential Circuits,” IEICE Transactions on Information and Systems, Vol.E87-D, No.3, pp.530-537, Mar. 2004.
  13. 小林真也, 久原俊介, 清家悠, 樋上喜信, “一般ユーザを対象とした自立負荷分散方式利用コマンドの実装,” 電気学会論文誌C, Vol.124, No.4, pp.1021-1028, 2004年4月.
  14. Y. Higami, S. Kajihara, H. Ichihara and Y. Takamatsu, “Test Cost Reduction for Logic Circuits: Reduction of Test Data Volume and Test Application Time,” Systems and Computers in Japan, Vol. 36, No. 6, pp. 69-83, June 2005.
  15. 高橋寛, 山本幸大, 樋上喜信, 高松雄三, ”BIST 環境における不確かなテスト集合による単一縮退故障の一診断法,” 電子情報通信学会論文誌D-I, Vol. J88-D-I, No. 6, pp.1029-1038, 2005年6月.
  16. 佐藤雄一, 高橋寛, 樋上喜信, 高松雄三, “検出/非検出情報に基づくオープン故障の一診断法,” 電子情報通信学会論文誌 D-I, Vol. J89-D-I, No. 4, pp. 778-787, 2006年4月.
  17. 樋上喜信, ケーワル K. サルージャ, 高橋寛, 小林真也, 高松雄三, “組合せ回路および順序回路に対する検出・非検出情報に基づく診断用テスト圧縮法,” 情報処理 学会論文誌, Vol. 47, No. 5, pp. 1269-1277, 2006年5月.
  18. Y. Higami, S. Kajihara, I. Pomeranz S. Kobayashi and Y. Takamatsu, “On Finding Don’t Cares in Test Sequences for Sequential Circuits,” IEICE Transactions on Information and Systems, Vol. E89-D, No. 11 , pp.2748-2755, Nov. 2006.
  19. Y. Higami, K. K. Saluja, H. Takahasi, S. Kobayashi, and Y. Takamatsu, “Fault Simulation and Test Generation for Transistor Shorts using Stuck-at Test Tools,” IEICE Transactions on Information and Systems, Vol. E-91-D, No. 3, pp. 690-699, Mar. 2008.
  20. Y. Takamatsu, H. Takahashi, Y. Higami, T. Aikyo, and K. Yamazaki “Fault Diagnosis on Multiple Fault Models by Using Pass/Fail Information,” IEICE Transactions on Information and Systems, Vol. E-91-D, No. 3, pp. 675-682, Mar. 2008.
  21. H. Takahashi, Y. Higami, S. Kadoyama, Y. Takamatsu, K. Yamazaki, T. Aikyo and Y. Sato “Post-BIST Fault Diagnosis for Multiple Faults,” IEICE Transactions on Information and Systems, Vol. E-91-D, No. 3, pp. 771-775, Mar. 2008.
  22. 樋上喜信, 藤尾昇平, 阿萬裕久, 高橋寛, 高松雄三, “ハードウェアテスト生成ツールを用いた組込みシステムに対するテストケース生成法,” 組込みシステムシンポジウム論文集, pp. 151-157, 2008年10月.
  23. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi and Y. Takamatsu, “Maximizing Stuck-open Fault Coverage Using Stuck-at Test Vectors,” IEICE Transactions on Fundamentals, Vol. E91-A, No. 12, pp. 3506-3513, Dec. 2008.
  24. S. Takasuka, K. Hirata, Y. Higami and S. Kobayashi, “Consideration of an Appropriate Program Segment Size on Method of Concealing Purposes of Processing,” Polish Journal of Environmental studies, Vol. 17, No. 4C, pp.221-225, 2008.
  25. K. Himeda, K. Hirata, Y. Higami and S. Kobayashi, “Consideration of Characteristics of Programs for concealing Purpose of Processing in Distributed Computing Systems,” Polish Journal of Environmental studies, Vol. 17, No. 4C, pp.226-229, 2008.
  26. H. Miyaoka, K. Hirata, Y. Higami and S. Kobayashi, “The Detection of Falsification with Check Codes in External Grid,” Polish Journal of Environmental studies, Vol. 17, No. 4C, pp.294-298, 2008.
  27. 相京隆, 高橋寛, 樋上喜信, 大津潤一, 小野恭平, 清水隆司, 高松雄三, “検出可能な遅延故障サイズを考慮した遅延故障診断法,” 電子情報通信学会論文誌D, Vol. J92-D, No. 7, pp. 984-993, 2009年7月.
  28. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi and Y. Takamatsu, “An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation,” IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp.250-262, Aug. 2009.
  29. K. Sugimoto, K. Hirata, Y. Higami and S. Kobayashi, “Multiplexing Scheme with distributed Processing in External Grids,” Polish Journal of Environmental Studies, Vol. 18, No. 4A, pp.50-53, 2009.
  30. K. Matsumura, K. Hirata, Y. Higami and S. Kobayashi, “An Effective Filtering Method Based on Occurrence Rates and consistency in Personalized Information Delivery Systems,” Polish Journal of Environmental Studies, Vol. 18, No. 4A, pp.54-58, 2009.
  31. T. Ooka, K. Hirata, Y. Higami and S. Kobayashi, “Information filtering Method Using Diversity among Languages for Personalized Information Delivery Systems,” Polish Journal of Environmental Studies, Vol. 18, No. 4A, pp.67-71, 2009.
  32. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi and Y. Takamatsu, “Addressing Defect Coverage through Generating Test Vectors for Transistor Defects,” IEICE Transactions on Fundamentals, Vol. E92-A, No. 12, pp. 3128-3135, Dec. 2009.
  33. K. Hirata, K. Kalegele, Y. Higami and S. Kobayashi, “Dynamic Parallel Downloading with Network Coding in λ–grid Networks,” Journal of Communications, Vol. 5, No. 5, pp. 425- 435, May 2010.
  34. K. Hirata, K. Kalegele, Y. Higami and S. Kobayashi, “Replica Selection and Downloading Based on Wavelength Availability in λ–grid Networks,” Journal of Communications, Vol. 5, No. 9, pp. 692-702, Sep. 2010.
  35. 山崎浩二, 堤利幸, 高橋寛, 樋上喜信, 相京隆, 四柳浩之, 橋爪正樹, 高松雄三, “故障励起関数を利用したオープン故障の診断法,” 電子情報通信学会論文誌D, Vol.J93-D, No.11, pp. 2416-2425, 2010年11月.
  36. 高松雄三, 佐藤康夫, 高橋寛, 樋上喜信, 山崎浩二, “[サーベイ論文] 論理回路の故障診断法 -外部出力応答に基づく故障箇所指摘法の発展-,”電子情報通信学会論文誌D, Vol. J94-D, No. 1, pp. 266-279, 2011年1月. (平成 23 年度論文賞受賞)
  37. Wardi, K. Hirata, Y. Higami and S. Kobayashi, “RE-OLSR: Residual Energy-Based OLSR Protocol in Mobile Ad Hoc Networks, “The International Journal of Multimedia Technology, Vol. 1, No. 2, pp. 93-97, Dec. 2011.
  38. Y. Higami, S. Ohno, H. Yamaoka, H. Takahashi, Y. Shimizu and T. Aikyo, “Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool,” IEICE Transactions Information and Systems, Vol. E95-D, No. 4, pp. 1093 – 1100, Apr. 2012.
  39. Dewiani, K. Hirata, K. Kalegele, Y. Higami and S. Kobayashi, “Dynamic Routing and Wavelength Assignment with Backward Reservation in Wavelength-routed Multifiber WDM Networks,” Journal of Networks, vol. 7, no. 9, 1441-1448, Sep. 2012.
  40. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment,” IEICE Transactions on Information and Systems, Vol.E96-D, No.6, pp. 1323-1331, June. 2013.
  41. 亀山修一, 馬場雅之, 樋上喜信, 高橋寛, “バウンダリテスト実行時のIC内部の擾乱,” 電子情報通信学会論文誌D, Vol. J96-D, No.9, pp.2078-2081, 2013年9月.
  42. Zulkufli Tahir, Tsutomu Inamoto, Yoshinobu Higami and Shin-ya Kobayashi, ”An Analysis Of Automated HTML5 Offline Services (AHOS),” Journal of Information and Communication Engineering, Vol. 1, No.1, pp. 9-15, 2015.
  43. 亀山修一, 馬場雅之, 樋上喜信, 高橋寛, “アナログバウンダリスキャンによる三次元積層後のTSV抵抗精密計測法,” 電子情報通信学会論文誌D, Vol. J97-D, No.4, pp.887-890, 2014年4月.
  44. T. Inamoto, Y. Higami, and S. Kobayashi, “Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs,” International Journal of Networking and Computing, vol. 4, no. 2, pp. 321-335, July 2014.
  45. 志田洋, 樋上喜信, 阿萬裕久, 高橋寛, ケーワル・サルージャ, “0-1整数計画問題を利用した欠陥検出向けテストパターン選択法,” 信頼性学会論文誌, Vol. 36, No. 8, pp. 501-507, 2014.
  46. S. Kameyama, M. Baba, Y. Higami and H. Takahashi, “Measuring Method for TSV-based Interconnect Resistance in 3D-SIC by Embedded Analog Boundary-Scan Circuit,” Transactions of the Japan Institute of Electronics Packaging, Vol. 7, No. 1, pp. 140-146, 2014.
  47. 志田洋, 大串裕郁, 樋上喜信, 阿萬裕久, 高橋寛, “設備故障が旅客に与える経済的損失を評価尺度とした鉄道信号設備のライフサイクルコストの低減に関する考察, 電子情報通信学会論文詩D, Vol. J99-D, No. 5, pp. 539-548, May. 2016.
  48. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays,” IPSJ Transactions on System LSI Design Methodology, Vol. 9, pp. 13-20, 2016.
  49. T. Inamoto, Y. Higami, and S. Kobayashi, "Road-map to Bridge Theoretical and Practical Approaches for Elevator Operation Problems," International Journal of Smart Computing and Artificial Intelligence, Vol. 1, No. 2, pp. 113-135, 2017.
  50. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja, "A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line," IEICE Trans. on Information and Systems, Vol. E100-D, No. 9, pp.2224-2227, 2017.
  51. Hiroyuki Yotsuyanagi, Kotaro Ise, Masaki Hashizume, Y. Higami, and H. Takahashi, "Discrimination of a resistive open using anomaly detection of delay variation induced by transitions on adjacent lines," IEICE Trans. on Fundamentals, Vol. E100-A, No. 12, pp. 2842-2850, 2017.
  52. Tsutomu Inamoto, Yoshinobu Higami, Shin-ya Kobayashi, “Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems,” IEICE Transactions 100-A(2): 385-394 (2017)
  53. Keiichi Endo, Gakuto Fujioka, Ayame Onoyama, Dai Okano, Yoshinobu Higami, and Shinya Kobayashi, "Evaluation of Educational Applications in Terms of Communication Delay between Tablets with Bluetooth or Wi-Fi Direct," Vietnam Journal of Computer Science, Vol. 5, No. 3, pp. 219-227, 2018.
  54. S. Wang, Y. Higami, H. Iwata, J. Matsushima and H. Takahashi, “Automotive Functional Safety Assurance by POST with Sequential Observation,” IEEE Design and Test of Computers, vol. 35, no. 3, pp. 39-45, Jan. 2018.
  55. Hanan T. Al-Awadhi, Tomoki Aono, S. Wang, Y. Higami, H. Takahashi, H. Iwata, Y. Maeda and J. Matsushima, “FF-Control Point Insertion (FF-CPI) to Overcome the Degradation of Fault Detection under Multi-Cycle Test for POST,” IEICE Trans. on Information and Systems, Vol. E103-D, No. 11, pp. 2289-2301, Nov. 2020.
  56. Tsutomu Inamoto and Yoshinobu Higami, “Formulation of a Test Pattern Measure that Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis,” IEICE Trans. on Fundamentals, Vol.E103-A, No.12, pp. 1456-1463, 2020.

国際会議

  1. Y. Higami, S. Kajihara, and K. Kinoshita, "Reduced Scan Shift : A New Testing Method for Sequential Circuits," Proceedings of IEEE International Test Conference, pp. 624-630, Oct. 1994.
  2. Y. Higami, S. Kajihara, and K. Kinoshita, "A Partial Scan Algorithm Based on Reduced Scan Shift," Proceedings of IEEE Third Asian Test Symposium, pp. 336-341, Nov. 1994.
  3. Y. Higami, S. Kajihara, and K. Kinoshita, "Test Sequence Compaction by Reduced Scan Shift and Retiming," Proceedings of IEEE Fourth Asian Test Symposium, pp. 169-175, Nov. 1995.
  4. Y. Higami, S. Kajihara, and K. Kinoshita, "Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique," Proceedings of IEEE Fifth Asian Test Symposium, pp. 94-99, Nov. 1996.
  5. Y. Higami and K. Kinoshita, "Design of Partially Parallel Scan Chain," Proceedings of IEEE European Design & Test Conference, p. 626, Mar. 1997.
  6. Y. Higami, T. Maeda and K. Kinoshita, “Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults,” Proceedings of IEEE International Workshop on IDDQ Testing, pp.12-16, Nov. 1997.
  7. Y. Higami, K. K. Saluja and K. Kinoshita, “Static Test Compaction for IDDQ Testing of Sequential Circuits,” Proceedings of IEEE International Workshop on IDDQ Testing, pp.9- 13 , Nov. 1998.
  8. Y. Higami, K. K. Saluja and K. Kinoshita, “Observation Time Reduction for IDDQ Testing of Bridging Faults in Sequential Circuits,” Proceedings of IEEE Seventh Asian Test Symposium, pp.312-317, Dec. 1998.
  9. Y. Higami, K. K. Saluja and K. Kinoshita, “Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits," Proceedings of IEEE International Conference on VLSI Design, pp.72-77, Jan. 1999.
  10. Y. Higami, K. K. Saluja, Y. Takamatsu and K. Kinoshita, “Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits," Proceedings of IEEE Eighth Asian Test Symposium, pp. 141-146, Nov. 1999.
  11. Y. Higami, K. K. Saluja, Y. Takamatsu and K. Kinoshita, “Fault Models and Test Generation for IDDQ Testing," Proceedings of Asia and South Pacific Design Automation Conference, pp. 509-514, Jan. 2000.
  12. Y. Higami, Y. Takamatsu and K. Kinoshita, “Test Sequence Compaction for Sequential Circuits with Reset States,” Proceedings of IEEE Ninth Asian Test Symposium, pp. 165-170, Dec. 2000.
  13. Y. Higami, N. and Y. Takamatsu, “Test Generation for Double Stuck-at Faults,” IEEE Asian Test Symposium, Proceedings of IEEE Tenth Asian Test Symposium, pp. 71-75, Nov. 2001.
  14. H. Takahashi, M. Phadoongidhi, Y. Higami, K. K. Saluja and Y. Takamatsu, “Simulation-based Diagnosis for Crosstalk Faults in Sequential Circuits,” Proceedings of IEEE Tenth Asian Test Symposium, pp.63-68, Nov. 2001.
  15. Y. Higami, S. Kobayashi and Y. Takamatsu, “Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," Proceedings of IEEE International Workshop on Electronic Design, Test and Applications, pp. 431-433, Jan. 2002.
  16. Y. Ito, S. Miyazaki, Y. Higami and S. Kobayashi, “Improvement and Evaluation of Autonomous Load Distribution Method,” Proceedings of International Conference on Advanced Computer System, Oct. 2002.
  17. Y. Higami, S. Kobayashi and Y. Takamatsu, “A Method to Reduce Power Dissipation during Test for Sequential Circuits,” Proceedings of IEEE Eleventh Asian Test Symposium, pp. 326- 331, Nov. 2002.
  18. Y. Higami, S. Kajihara, I. Pomeranz, S. Kobayashi and Y. Takamatsu, “A Method to Find Don’t Care Values in Test Sequences for Sequential Circuits,” Proceedings of IEEE International Conference on Computer Design, pp. 397-399, Oct. 2003.
  19. K. Kashiwagi, Y. Higami and S. Kobayashi, “Improvement of the Processors Operating Ratio in Task Scheduling using the Deadline Method Parallel computing,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2003.
  20. Y. Higami, M. Sato, H. Takahashi, S. Kobayashi and Y. Takamatsu, “Acceleration Techniques for Crosstalk Fault Simulation,” Proceedings of International Multi-Conference on Advanced Computer Systems & Computer Information Systems and Industrial Management, pp. 300-309, June 2004.
  21. K. Kashiwagi, Y. Murata, Y. Higami and S. Kobayashi, “Improvement of List-Scheduling with Task Reallocation,” Proceedings of International Multi-Conference on Advanced Computer Systems & Computer Information Systems and Industrial Management, pp. 310-318, June 2004.
  22. K. Mizuno, K. Kashiwagi, Y. Higami and S. Kobayashi, “Virtual Circuit of Adaptability to Load Change with Using Multiagent,” Proceedings of International Multi-Conference on Advanced Computer Systems & Computer Information Systems and Industrial Management, pp. 346-355, June 2004.
  23. K. Motoyama, K. Kashiwagi, Y. Higami and S. Kobayashi, “Model Description Method for a Queuing Network Evaluation System,” Proceedings of International Multi-Conference on Advanced Computer Systems & Computer Information Systems and Industrial Management, pp. 372-379, June 2004.
  24. Y. Higami, S. Kajihara, S. Kobayashi and Y. Takamatsu, “Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Dissipation, Proceedings of IEEE Thirteenth Asian Test Symposium, pp. 46-49, Nov. 2004.
  25. H. Takahashi, Y. Yamamoto, Y. Higami and Y. Takamatsu, “Enhancing BIST Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set,” Proceedings of IEEE Thirteenth Asian Test Symposium, pp. 216-212, Nov. 2004.
  26. Y. Sato, H. Takahashi, Y. Higami and Y. Takamatsu , “Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests,” Proceedings of IEEE Thirteenth Asian Test Symposium, pp. 222-227, Nov. 2004.
  27. Y. Takamatsu, T. Seiyama, H. Takahashi, Y. Higami and K. Yamazaki, “On the Fault Diagnosis in the Presence of Unknown Fault Models Using Pass/Fail Information,” Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2987-2990, June 2005.
  28. K. Motoyama, K. Kashiwagi, Y. Higami and S. Kobayashi, “Model Description Method Based on a Graphical Language and a Character Based Language Together for a Queuing Network Model,” Proceedings of IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp. 93-96, Aug. 2005.
  29. S. Kobayashi, S. Morigaki, E. Nelson, K. Kashiwagi and Y. Higami, “Code Migration Concealment by Interleaving Dummy Segments,” Proceedings of IEEE Pacific Rim Conference on communications, Computers and signal Processing, pp. 269-272, Aug. 2005.
  30. H. Takahashi, Y. Yamamoto, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Aikyo and Y. Sato, “Post-BIST Fault Diagnosis for Multiple Stuck-at Faults,” Proceedings of IEEE International Workshop on Silicon Debug and Diagnosis, pp. 1-6, Nov. 2005.
  31. Y. Higami, K. K. Saluja, H. Takahashi, S. Kobayashi and Y. Takamatsu, “Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 659-664, Jan. 2006.
  32. H. Takahashi, S. Kadoyama, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Aikyo and Y. Sato, “Effective Post-BIST Fault Diagnosis for Multiple Faults,” Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 401-409, Sep. 2006.
  33. M. Kudo, K. Kashiwagi, Y. Higami and S. Kobayashi, “Reliability of Node Information on Autonomous Load Distribution Method,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2006.
  34. Y. Kinoshita, K. Kashiwagi, Y. Higami and S. Kobayashi, “Concealing the Purpose of Processing for Programs,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2006.
  35. Y. Hatano, K. Kashiwagi, Y. Higami and S. Kobayashi, “Improvement of Delivery Network Flow Control in Consideration of Cost and Transport Time,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2006.
  36. K. Kashiwagi, Y. Higami and S. Kobayashi, “A Consideration of Processor Utilization on Multi-Processor System,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2006.
  37. Y. Higami, K. K. Saluja, H. Takahasi, K. Kobayashi and Y. Takamatsu, “Diagnosis of Transistor Shorts in Logic Test Environment,” Proceedings of IEEE Fifteenth Asian Test Symposium, pp. 354-359, Nov. 2006.
  38. Y. Higami, K. K. Saluja, H. Takahasi, and Y. Takamatsu, “Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation,” Proceedings of IEEE International Conference on VLSI Design, Jan. 2007.
  39. H. Takahashi, Y. Higami, T. Kikkawa, T. Aikyo, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyamnagi and M. Hashizume, “Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines,” Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 243-251, Sep. 2007.
  40. T. Aikyo, H. Takahashi, Y. Higami, J. Ootsu, K. Ono and Y. Takamatsu, “Timing-Aware Diagnosis for Small Delay Defects,” Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 223-231, Sep. 2007.
  41. Y. Higami, K. K. Saluja, H. Takahasi, K. Kobayashi and Y. Takamatsu, “Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator,” Proceedings of IEEE Sixteenth Asian Test Symposium, pp. 271-274, Oct. 2007.
  42. H. Takahashi, Y. Higami, S. Kadoyama, T. Aikyo, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi and M. Hashizume, “Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines,” Proceedings of IEEE Sixteenth Asian Test Symposium, pp. 39-44, Oct. 2007.
  43. T. Goda, Y. Higami and S. Kobayashi, “Influence of Arrival of Tasks in Partial Nodes in a System on Autonomous Load Distribution Method,” Proceedings of International Conference on Advanced Computer Systems, Oct. 2007.
  44. M. Hashizume, H. Yotsuyanagi, T. Tsutsumi, K. Yamazaki, Y. Higami, H. Takahashi and Y. Takamatsu, “Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device,” Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 249-252, June 2008.
  45. S. Takasuka, K. Hirata, Y. Higami and S. Kobayashi, “Consideration of an Appropriate Program Segment Size on Method of Concealing Purposes of Processing,” International Conference on Advanced Computer Systems, Oct. 2008.
  46. H. Miyaoka, K. Hirata, Y. Higami and S. Kobayashi, “The Detection of Falsification with Check Codes in External Grid,” International Conference on Advanced Computer Systems, Oct. 2008.
  47. K. Himeda, K. Hirata, Y. Higami and S. Kobayashi, “Consideration of Characteristics of Programs for Concealing Purpose of Processing in Distributed Computing Systems,” International Conference on Advanced Computer Systems, Oct. 2008.
  48. Y. Higami, K. K. Saluja, H. Takahashi, K. Kobayashi and Y. Takamatsu, “Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults,” Proceedings of IEEE Seventeenth Asian Test Symposium, pp. 97-102, Nov. 2008.
  49. H. Yotsuyamagi, M. Hashizume, T. Tsutsumi, K. Yamazaki, T. Aikyo, Y. Higami, H. Takahashi and Y. Takamatsu, “Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90nm IC,” Proceedings of IEEE International Conference on VLSI Design, pp.91-96, Jan. 2009.
  50. K. Yamazaki, T. Tsutsumi, H. Takahashi, Y. Higami, T. Aikyo, H. Yotsuyamagi, M. Hashizume and Y. Takamatsu, “A Novel Approach for Improving the Quality of Open Fault," Proceedings of IEEE International Conference on VLSI Design, pp.85-90, Jan. 2009.
  51. K. Matsumura, K. Hirata, Y. Higami and S. Kobayashi, “An Effective Filtering Method Based on Occurrence Rates and Consistency in Personalized Information Delivery Systems,” International Conference on Advanced Computer Systems, Oct. 2009.
  52. T. Ooka, K. Hirata, Y. Higami and S. Kobayashi, “Information Filtering Method Using Diversity among Languages for Personalized Information Delivery Systems,” International Conference on Advanced Computer Systems, Oct. 2009.
  53. K. Sugimoto, K. Hirata, Y. Higami and S. Kobayashi, “Multiplexing Scheme with Distributed Processing in External Grids,” International Conference on Advanced Computer Systems, Oct. 2009.
  54. Y. Higami, Y. Kurose, S. Ohno H. Yamaoka, H. Takahashi, Y. Shimizu, T. Aikyo and Y. Takamatsu, “Diagnostic Test Generation for Transition Faults Using a Stuck-at ATPG Tool,” Proceedings of IEEE International Test Conference, Paper 16.3, Nov. 2009.
  55. H. Takahashi, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi and M. Hashizume, “New Class of Tests for Open Faults with Considering Adjacent Lines”, Proceedings of IEEE Eighteenth Asian Test Symposium, pp. 301-306, Nov. 2009.
  56. K. Hirata, Y. Higami and S. Kobayashi, “An Effective Dynamic Parallel Downloading Scheme with Network Coding in λ–grid Networks,” Proceedings of IEEE First Asian Himalayas International Conference on Internet, pp. 1-5, Nov. 2009.
  57. K. Manabe, Y. Yamada, H. Yotsuyanagi, T. Tsutsumi, K. Yamazaki, Y. Higami, H. Takahashi, M. Hashizume, “Output Voltage Estimation of a Floating Interconnect Line Caused by a Hard Open in 90nm ICs,” Proceedings of International Symposium on Communication and Information Technology, pp. 603-608, Oct. 2010.
  58. H. Takahashi, Y. Higami, Y. Takamatsu, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi and M. Hashizume, “A Method for Diagnosing Resistive Open Faults with Considering Adjacent Lines,” Proceedings of International Symposium on Communication and Information Technology, pp. 609-614, Oct. 2010.
  59. Wardi, K. Hirata, Y. Higami, and S. Kobayashi, "Energy Aware MPR Selection Mechanism in OLSR-based Mobile Ad Hoc Networks," Proceedings of International Conference on Advanced Computer Systems, Oct. 2010.
  60. A. Funo, K. Hirata, Y. Higami, and S. Kobayashi, "Optimistic Processing Protocol for Multiplexing in External PC Grids," Proceedings of International Conference on Advanced Computer Systems, Oct. 2010.
  61. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Fault Simulation and Test Generation for Clock Delay Faults,” Proceedings of Asia and South Pacific Design Automation Conference, pp. 799-805, Jan. 2011.
  62. K. Manabe, H. Yotsuyanagi, T. Tsutsumi, K. Yamazaki, Y. Higami, H. Takahashi, Y. takamatsu and M. Hashizume, “Estimation of Faulty Effects Caused by a Clack at an Interconnect Line in 90nm ICs,” Proceedings of International Conference on Electronics and Packaging, pp. 737-742, Apr. 2011.
  63. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Enhancement of Clock Delay Faults Testing,” Proceedings of IEEE European Test Symposium, p. 216, May 2011.
  64. Wardi, K. Hirata, Y. Higami and S. Kobayashi, “Residual Energy-based OLSR in Mobile Ad hoc Networks,” Proceedings of IEEE International Conference on Multimedia Technology, pp. 3214-3217, July 2011.
  65. Dewiani, K. Hirata, Y. Higami and S. Kobayashi, “Wavelength Selection Based on Wavelength Availability in Multi-fiber WDM Networks,” Proceedings of IEEE International Conference on Multimedia Technology, pp. 3794-3797, July 2011.
  66. Dewiani, K. Hirata, Y. Higami and S. Kobayashi, “Dynamic Routing and Wavelength Assignment Scheme using Signaling of Backward Reservation in Multifiber WDM Networks,” Proceedings of 2nd IEEE International Conference on ICT Convergence, pp. 447-452, Sep. 2011.
  67. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “On Detecting Transition Faults in the Presence of Clock Delay Faults,” Proceedings of IEEE Twentieth Asia Test Symposium, pp. 1-6, Nov. 2011.
  68. Y. Higami, H. Furutani, T. Sakai, S. Kameyama and H. Takahashi, “Test Pattern Selection for Defect-Aware Test,” Proceedings of IEEE Twentieth Asia Test Symposium, pp. 102-107, Nov. 2011.
  69. Dewiani, K. Hirata, K. Kalegele, Y. Higami and S. Kobayashi, “Dynamic Routing and Wavelength Assignment in Multifiber WDM Networks with Sparse Wavelength Conversion,” Proceedings of the 3rd IEEE International Conference on ICT Convergence, pp. 567-572, Oct. 2012.
  70. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis of Bridging Faults at Gated Clock Lines,” Proceedings of The 27th International Technical Conference on Circuits/Systems, Computers and Communications, July 2012.
  71. H. Takahashi, Y. Higami, K. Yamazaki, T. Tsutsumi, H. Yotsuyanagi and M. Hashizume, “Test Generation for Resistive Open Faults with Considering Adjacent Lines,” Proceedings of The 27th International Technical Conference on Circuits/Systems, Computers and Communications, July 2012.
  72. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis for Bridging Faults on Clock Lines,” Proceedings of Pacific Rim International Symposium on Dependable Computing, pp. 135-144, Nov. 2012.
  73. K. Yamazaki, T. Tsutsumi, H. Takahashi, Y. Higami, H. Yotsuyanagi, M. Hashizume and K. K. Saluja, “Diagnosing Resistive Open Faults Using Small Delay Fault Simulation,” Proceedings of IEE Twenty-first Asian Test Symposium, Nov. 2013.
  74. T. Inamoto, Y. Higami, and S. Kobayashi, “Injecting Speculation on Ideal Trajectories into a Trip-based Integer Programming Model for Elevator Operations,” Proceedings of IEEE 2nd Global Conference on Consumer Electronics, pp. 23-27, Oct. 2013.
  75. J. Yamashita, H. Yotsuyanagi, M. Hashizume, Y. Higami and H. Takahashi, “On SAT-based Test Generation for Observing Delay Variation Caused by a Resistive Open Fault and Its Adjacent Lines,” The Fourteenth International Workshop on RTL and High Level Testing, Nov. 2013.
  76. S. Kameyama, M. Baba, Y. Higami and H. Takahashi, “Accurate Resistance Measuring Method for High Density Post-Bond TSVs in 3D-SIC with Electrical Probes,” Proceedings of International Conference on Electronics Packaging, Apr. 2014.
  77. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis of Delay Faults in Multi-Clock SOCs,” Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 217-220, July 2014.
  78. Y. Higami, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp. 320-325, July 2014. (Best Paper Award 受賞)
  79. T. Inamoto, Y. Higami, and S. Kobayashi, “Decreasing Computational Times for Solving Static Elevator Operation Problems by Assuming Maximum Waiting Times,” IEEE 3rd Global Conference on Consumer Electronics, pp. 593—596, Oct. 2014.
  80. J. Yamashita, H. Yotsuyanagi, M. Hashizume, Y. Higami and H. Takahashi, “On SAT-based Test Generation for Resistive Open Using Delay Variation Caused by Effect of Adjacent Lines,” The Fifteenth International Workshop on RTL and High Level Testing, Nov. 2014.
  81. K. Mavlonov, Y. Higami, and S. Kobayashi, “Sushi: A Lightweight Distributed Image Storage System for Mobile and Web Services,” International Conference on Advanced Computer Systems, 2014.
  82. T. Inamoto, Y. Higami, and S. Kobayashi, “A Call-based Integer Programming Model for Static Elevator Operation Problems,” The 7th International Conference on Soft Computing and Intelligent Systems & The 15th International Symposium on Advanced Intelligent Systems, Dec. 2014.
  83. H. Shida, H. Oogushi, Y. Higami, H. Aman and H. Takahashi, “A Proposal of Maintenance Cost Model of Track Circuits, “The Ninth International Conference on Mathematical Methods in Reliability, June 2015.
  84. S. Wang, T. Inoue, H. T. Al-Awadhi, Y. Higami and H. Takahashi, “A Simulated Annealing based Pattern Selection Method to Handle Power Supply Noise for Resistive Open Fault Diagnosis,” Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 592-595, July 2015.
  85. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis for Delay Faults in the Presence of Clock Delays Considering Hazards,” Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications, pp. 649-652, July 2015.
  86. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja, “Diagnosis of Delay Faults Considering Hazards,” Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp. 503-508, July 2015.
  87. T. Inamoto, Y. Higami and S. Kobayashi, “POP-based Approximation Method Enabled by Physical ILP Model for Static Elevator Operation Problems,” 22nd International Symposium on Mathematical Programming, July 2015.
  88. Z. Tahir, T. Inamoto, Y. Higami, and S. Kobayashi, “An Automated HTML5 Offline Services (AHOS) A Case Study of Web-based Maintenance DSS in SMIs,” Proceedings of International Conference on Quality in Research, Aug. 2015.
  89. Tsutomu Inamoto, Yoshinobu Higami, and Shinya Kobayashi, “Giving Formal Roles to Elevators for Breaking Symmetry in Static Elevator Operation Problems,” Proc. IEEE Global Conference on Consumer Electronics, Oct. 2015.
  90. Z. Tahir, T. Inamoto, Y. Higami, and S. Kobayashi: “The Analysis of Automated HTML5 Offline Services (AHOS),” The International Conference on Intelligent Informatics and Biomedical Sciences (ICIIBMS) 2015.
  91. K. Mavlonov, T. Inamoto, Y. Higami, and S. Kobayashi: “Design and Implementation of Data Synchronization and Offline Capabilities in Native Mobile Apps,” 8th Asian Conference on Intelligent Information and Database Systems (ACIIDS) 2016.
  92. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja, “Multi-Cycle Test Diagnosis for Path Delay Variations,” Taiwan and Japan Conference on Circuits and Systems, July 2016. (S1A.5)
  93. Keiichi Endo, Ayama Onoyama Dai Okano, Yoshinobu Higami and Sinya Kobayashi, “Comparative Evaluation of Bluetooth and Wi-Fi Direct for Tablet-Oriented Educational Applications,” Asian Conference on Intelligent Information and Database Systems (ACIIDS), Apr. 2017.
  94. H. Al-Awadhi, S. Wang, Y. Higami and H. Takahashi, "Pattern Partitioning based Field Testing for Improving the Detection Latency of Aging-Induced Delay Faults," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 21-24, July 2017. (OS-01-01)
  95. Y. Higami, S. Wang, H. Takahashi and K. K. Saluja, "Adaptive Field Diagnosis for Reducing the Number of Test Patterns," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 412-415, July 2017. (OS-13-05)
  96. Yuuya Ohama, H. Yotsuyanagi, M. Hashizume, Y. Higami and H. Takahashi, "On Selection of Adjacent Lines in Test Pattern Generation for Delay Faults Considering Crosstalk Effects," Proc. 17th International Symposium on Communications and Information Technologies, pp. 92-96, Sept. 2017.
  97. Yoichi Maeda, Hiroyuki Iwata, Jun Matsushima, S. Wang, Y. Higami, and H. Takahashi, "Towards an ISO26262 Compliant DFT Architecture Enabling POST for Ultra-Large-Scale Automotive MCU," Proc. 2nd IEEE Int. Workshop on Automotive Reliability & Test, Nov. 2017. (Session 1)
  98. T. Inamoto and Y. Higami, "Harnessing Fuzziness of the Pragmatic Rule-Design without IF-THEN Rules", Proc. The 3rd Int. Conf. on Fuzzy Systems and Data Mining," Nov. 2017.
  99. S. Wang, Y. Higami, H. Takahashi, Masayuki Sato Mitsunori Katsu and Shoichi Sekiguchi, "Testing of Interconnect Defects in Memory based Reconfigurable Logic Device (MRLD)," Proc. Asian Test Sympo., Nov. 2017.
  100. Senling Wang, Tomoki Aono, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi, Mitsunori Katsu, and Shoichi Sekiguchi, "Testing of Interconnect Defects in Memory based Reconfigurable Logic Device (MRLD)," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 25-28 (CS-02), July 2018.
  101. Yoshinobu Higami, Tsutomu Inamoto, Senling Wang, Hiroshi Takahashi, and Kewal K Saluja, "Fault Diagnosis Considering Path Delay Variations in Multi Cycle Test Environment," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 90-93 (CS-05), July 2018.
  102. K. Endo, G. Fujioka, A. Onoyama, D. Okano, Y. Higami, and S. Kobayashi, "Evaluation of educational applications in terms of communication delay between tablets with Bluetooth or Wi-Fi Direct," Vietnam Journal of Computer Science, 2018.
  103. Senling Wang, Tomoki Aono, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Yoichi Maeda, and Jun Matsushima, "Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST," Proc. Asian Test Sympo., pp. 155-160, 2018.
  104. Tsutomu Inamoto and Yoshinobu Higami, "Application of Convolutional Neural Networks to Regenerate Deterministic Test Pattern for BIST," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 523-524 (OS-26), June 2019.
  105. Yoshinobu Higami, Tomokazu Nakamura, Tsutomu Inamoto, Senling Wang, Hiroshi Takahashi, and Kewal K Saluja, "Compact Dictionaries for Reducing Compute Time in Adaptive Diagnosis," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 525-528 (OS-26), June 2019.
  106. Senling Wang, Hanan T. Al-Awadhi, Tomoki Aono, Yoshinobu Higami, and Hiroshi Takahashi, "Feasibility of Machine Learning Algorithm for Test Partitioning," Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 529-532 (OS-26), June 2019.
  107. Yoshinobu Higami, Tsutomu Inamoto, Senling Wang, Hiroshi Takahashi, Kewal K. Saluja, “Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application,” Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 131-136 (4B-1), June 2020.
  108. Tsutomu Inamoto, Yoshinobu Higami, “Regeneration of Test Patterns for BIST by Using Artificial Neural Networks,” Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 137-140 (4B-2), June 2020.
  109. Xihong Zhou, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, “Aging Monitoring for Memory-Based Reconfigurable Logic Device (MRLD) ,” Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications, pp. 228-233 (5B-5), June 2020.

総説・解説等

【解説記事】
  1. 樋上喜信, 高橋寛, “(研究最前線) ブリッジ故障とクロストーク故障に対するテスト,” 電子情報通信学会情報システム・ソサイエティ誌, Vol. 8, No. 4, pp. 9-11, 2004年2月.
【招待講演】
  1. Y. Higami, “Sequential Circuit Test Generation for IDDQ Testing of Bridging Faults,” Computer Engineering Seminar in Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Nov. 1997.
  2. Y. Higami, K. K. Saluja, Y. Takamatsu and K. Kinoshita, “Fault Models and Test Generation for IDDQ Testing," Embedded Tutorial in Asia and South Pacific Design Automation Conference, Jan. 2000.
  3. 樋上喜信, “デジタル回路とLSI設計検証入門-論理回路の製造テスト,” 第33回九州工業大学情報技術セミナー, 2003年6月.
  4. Y. Higami, “Test and Diagnosis of Transistor Shorts in Logic Circuits,” Computer Engineering Seminar in Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Sep. 2006.
  5. 樋上喜信, “故障するコンピュータと故障しないコンピュータ,” 伊予高校出張講義, 2007年8月.
  6. 樋上喜信, “テスト技術最新動向 (上流からのテスト設計),” 第27回STARCアドバンスト講座テスト技術セミナー, 2007年12月.
  7. 樋上喜信, “故障するコンピュータと故障しないコンピュータ, ”上浮穴高校出張講義, 2009年8月.
  8. Y. Higami, "Test Generation Methods for Delay Faults on Clock Lines," Proc. The 3rd Int. Conf. on Fuzzy Systems and Data Mining, Nov. 2017.
  9. Y. Higami, "Fault Simulation using Hazard Signals and Its Application to Fault Diagnosis for Delay Faults," Proc. Int. Conf. for Top and Emerging Computer Scientists, Dec. 2017.
  10. Y. Higami, "Adaptive Field Diagnosis for Reducing Computing time," 4th Int. Conf. on Fuzzy Systems and Data Mining, Nov. 2018.

特許

  1. Fault test apparatus and method for testing semiconductor device under test using fault 
excitation function, United States Patent 7983858, July 19, 2011, Filed Aug. 21, 2008, Inventors: Yuzo Takamatsu, Hiroshi Takahashi, Yoshinobu Higami, Michinobu Nakao, Takashi Aikyo, Michiaki Emori and Hideo Ohmae, Assignee: Semiconductor Technology Academic Research Center.
  2. 故障推定装置及び方法, 特願2010-91488・2010年4月12日出願・特開2010-204107・2010 年9月16日公開, 2012年10月5日登録, 特許第5103501号, 発明者:高松雄三, 高橋寛, 樋上喜信, 中尾教伸, 相京隆, 江守道明, 大前英雄, 出願人:株式会社半導体理工学研究センター.

外部資金獲得状況

【科学研究費】
  1. 順序回路に対するテスト系列生成とテスト容易化設計, 科学研究費補助金特別研究員奨励費, 代表, 1996年4月~1999年3月.
  2. 超高速・超微細VLSIに対する組込み自己テスト手法と故障診断法に関する研究, 科学研究費補助金基盤研究 (C)(2), 分担, 2003年4月~2006年3月.
  3. 組み込みシステムに対するソフト/ハード協調テスト法の開発, 科学研究費補助金基盤研究 (C), 分担, 2006年4月~2009年3月.
  4. 高速VLSIのクロストーク故障に対する高信頼テスト手法に関する研究, 科学研究費補助金基盤研究 (C), 代表, 2007年4月~2010年3月.
  5. システムLSIにおけるクロック信号線上の故障に対する検査法・診断法の開発, 科学研究費補助金基盤研究 (C), 代表, 2010年4月~2013年3月.
  6. 3次元LSIにおけるビア接続不良に対するテストと診断に関する研究, 科学研究費補助金基盤研究 (C), 代表, 2013年4月~2016年3月.
  7. 高精度遅延故障シミュレータを用いた遅延故障に対するテストと診断に関する研究，科学研究費助成事業基盤研究 (C)，代表，2016年4月～2020年3月.
  8. アダプティブ故障診断における故障診断時間の短縮に関する研究，科学研究費助成事業基盤研究 (C)，代表，2019年4月～2022年3月.
  9. つながるデバイスのフィールドテストのための信頼性強化設計法の開発，科学研究費助成事業基盤研究 (C)，分担，2019年4月～2022年3月.
【共同研究・受託研究・研究助成】
  1. SOCの設計とテストに関する研究, シャープ株式会社との共同研究, 分担, 1996年4月~2009年3月.
  2. Test Sequence Compaction for Sequential Circuits with Reset States, 財団法人C&C振興財団国際会議発表助成, 代表, 2000年11月.
  3. BIST環境に適した故障診断法に関する研究, 株式会社半導体理工学研究センタとの共同研究, 分担, 2003年4月~2006年3月.
  4. テストチップの制作とその解析に基づく製造容易化設計のための新故障モデルとそのテスト・故障診断に関する研究, 株式会社半導体理工学研究センタとの共同研究, 分担, 2006年4月~2009年3月.
  5. 遅延故障診断に関する研究, 株式会社半導体理工学研究センタとの共同研究, 分担, 2007年4月~2009年3月.
  6. ゲートレベルツールを用いたトランジスタレベル故障診断法の開発, 独立行政法人科学技術振興機構シーズ発掘試験受託研究, 代表, 2007年8月~2008年3月.
  7. トランジスタ不良に伴う遅延故障に対する故障検査法の開発, 独立行政法人科学技術振興機構シーズ発掘試験受託研究, 代表, 2008年8月~2009年3月.
  8. 超高信頼性チップ製造のためのシグナルインティグリティ不良のモデル化およびその故障検査法, 株式会社半導体理工学研究センタとの共同研究, 分担, 2009年4月~2012年3月.
  9. 愛南町における養殖現場と連携した双方向『水産情報コミュニケーションシステム』の開発に向けた研究, 愛媛大学COC地域志向教育研究経費, 分担, 2014年12月~2015年3月.
  10. 養殖現場と連携した双方向『水産情報コミュニケーションシステム』による赤潮・魚病対策技術の開発, 総務省戦略的情報通信研究促進事業 (SCOPE) 地域ICT振興型研究開発, 分担, 2015年6月~2019年3月.
  11. 高精度遅延故障シミュレータを用いた遅延故障に対するテストと診断に関する研究, 科学研究費助成事業基盤研究(C), 代表, 平成28年4月~平成31年3月.
  12. 機能安全技術のための組込み自己診断法の開発, 科学研究費助成事業基盤研究(C), 分担, 平成28年4月~平成31年3月.
  13. その他, 共同研究3件, 国際会議発表助成1件.

学会での活動

  1. FTC (フォールトトレラントコンピュータ) 研究会, 事務局担当, 1998年8月～2009年1月.
  2. 電子情報通信学会, 査読委員, 1998年5月～現在.
  3. IEEE Asian Test symposium, 実行委員, 2001年1月～2002年11月.
  4. ACM主催国際大学対抗プログラミングコンテスト愛媛大学, 現地実行委員, 2004年11月.
  5. IEEE Asian Test Symposium, プログラム委員, 2006年5月～2006年11月.
  6. 電子情報通信学会, 英文誌D「VLSIのテストと検証」特集号編集委員, 2003年3月～2004年3月.
  7. 電子情報通信学会, 英文誌D「VLSIのテストと検証」特集号編集委員, 2007年3月～2008年3月.
  8. 電子情報通信学会, 英文誌D編集委員, 2007年5月～2011年5月.
  9. 情報処理学会, SLDM研究会運営委員, 2008年4月～2012年3月.
  10. IEEE Asian Test symposium, 実行委員, 2008年11月.
  11. 電子情報通信学会, 英文誌D「SOCのテスト・診断・検証」特集号編集幹事, 2008年4月～2010年1月.
  12. 電子情報通信学会, 英文誌D「多値論理とVLSIコンピューティング」特集号編集幹事, 2009年4月～2010年9月.
  13. 情報処理学会, 四国支部幹事, 2010年4月～2012年5月.
  14. 電子情報通信学会, 英文誌A編集委員, 2011年5月～現在.
  15. 電気関係学会四国支部連合大会, 実行委員, 2011年9月.
  16. 電子情報通信学会, 英文誌A「VLSI設計とCADアルゴリズム」特集号編集幹事, 2012年3月～2012年12月.
  17. 電子情報通信学会, 英文誌A「VLSI設計とCADアルゴリズム」特集号編集幹事, 2013年3月～2013年12月.
  18. IEEE Asian Test Symposium, プログラム委員, 2013年11月.
  19. 電子情報通信学会, 英文誌A「VLSI設計とCADアルゴリズム」特集号編集幹事, 2014年3月～2014年12月.
  20. 情報処理学会 Transactions on System LSI Design Methodology 編集委員, 2014年5月～.
  21. IEEE Asian Test Symposium, プログラム委員, 2014年11月.
  22. 電子情報通信学会, 英文誌A「VLSI設計とCADアルゴリズム」特集号編集委員, 2015年3月~2015年12月.
  23. IEEE Shikoku Section Professional Activities Chair, 2015年3月～2016年2月.
  24. 情報処理学会・電子情報通信学会主催 第14回情報技術フォーラム (FIT2015) 現地実行委員, 2015年3月～2015年9月.
  25. 電子情報通信学会, 英文誌A「SoC設計手法」特集号編集委員, 2015年9月～2016年7月.
  26. IEEE Asian Test Symposium 実行委員, 2015年1月～2016年11月.
  27. 電子情報通信学会, 英文誌A「VLSI設計とCADアルゴリズム」特集号編集委員, 2016年3月～2016年12月.
  28. 電子情報通信学会, 英文誌A「SoC設計手法」特集号編集委員, 2016年9月～2017年7月.
  29. 情報処理学会四国支部 委員, 2016年6月～2018年6月.
  30. IEEE Asian Test Symposium プログラム委員，2020年5月～2020年11月
  31. IEEE Asian Test Symposium プログラム委員長，2020年8月～2021年11月
  32. 情報処理学会全国大会 現地実行委員長，2021年3月～2022年3月

連絡先

  • 居室: 工学部5号館10階 10-5
  • メールアドレス: higamicsmail