Publications

発表論文（主要な論文のみ）

2022年度

  1. Y. Higami, T. Yamauchi, T. Inamoto, S. Wang, H. Takahashi, and K.K. Saluja: "Machine Learning Based Fault Diagnosis for Stuck-at Faults and Bridging Faults," Proc. International Technical Conference on Circuits/Systems Computers and Communications, 2022.
  2. T. Inamoto, T. Nishino, S. Wang, Y. Higami, and H. Takahashi: "Preliminary Study on Noise-Resilient Artificial Neural Networks for On-Chip Test Generation," Proc. 2022 IEEE 11th Global Conference on Consumer Electronics (GCCE), pp.574-578, 2022.

2021年度

  1. Y. Higami, T. Nakamura, T. Inamoto, S. Wang, H. Takahashi, and K.K. Saluja: "Compaction of Fault Dictionary without Degrading Diagnosis Ability," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 2021.
  2. T. Inamoto, K. Ohtomo, and Y. Higami: "Preliminary Evaluation of Artificial Neural Networks as Test Pattern Generators for BIST," Proc. International Technical Conference on Circuits/Systems Computers and Communications, pp.307-310, 2021.

2020年度

  1. T. Inamoto, and Y. Higami, "Formulation of a Test Pattern Measure that Counts Distinguished Fault-Pairs for Circuit Fault Diagnosis," IEICE Transactions on Fundamentals, Vol. E103-A, No. 12, pp. 1456-1463, 2020.
  2. Y. Higami, T. Inamoto, S. Wang, H. Takahashi, and K. Saluja, "Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 131-136, 2020.
  3. T. Inamoto, and Y. Higami, "Regeneration of Test Patterns for BIST by Using Artificial Neural Networks," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 137-140, 2020.

2019年度

  1. T. Inamoto, Y. Higami, and K. Sakakibara, "Bridge-Aware Grid-Clustering Integer Linear Programming Formulation for Traveling Salesman Problem," Proc. SICE Annual Conference 2019, pp. 130-135, 2019.
  2. T. Inamoto, and Y. Higami, "Application of Convolutional Neural Networks to Regenerate Deterministic Test Pattern for BIST," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 523-524, 2019.
  3. Y. Higami, T. Nakamura, T. Inamoto, S. Wang, H. Takahashi, and K. Saluja, "Compact Dictionaries for Reducing Compute Time in Adaptive Diagnosis," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 525-528, 2019.

2018年度

  1. T. Inamoto, and Y. Higami, "Investigation on Pragmatic Rule-Bases for Imitating Artificial Neural Networks by Using the Mountain-Car Problem," Proc. The Twenty-Fourth International Symposium on Artificial Life and Robotics 2019 (AROB 24th 2019), pp. 351-356, 2019.
  2. Y. Higami, "Adaptive Field Diagnosis for Reducing Computing Time," Proc. 4th International Conference on Fuzzy Systems and Data Mining, 2018.
  3. Y. Higami, T. Inamoto, S. Wang, H. Takahashi, and K. Saluja, "Fault Diagnosis Considering Path Delay Variations in Multi Cycle Test Environment," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 90-93, 2018.

2017年度

  1. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi, and K. Saluja, "A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line," IEICE Transactions on Information and Systems, Vol. E100-D, No. 9, pp. 2224-2227, 2017.
  2. T. Inamoto, Y. Higami, and S. Kobayashi, "Road-map to Bridge Theoretical and Practical Approaches for Elevator Operation Problems," International Journal of Smart Computing and Artificial Intelligence, Vol. 1, No. 2, pp. 113-135, 2017.
  3. Y. Higami, "Test Generation Methods for Delay Faults on Clock Lines," Proc. The 3rd International Conference on Fuzzy Systems and Data Mining, 2017.
  4. T. Inamoto, and Y. Higami, "Harnessing Fuzziness of the Pragmatic Rule-Design without IF-THEN Rules," Proc. The 3rd International Conference on Fuzzy Systems and Data Mining, 2017.
  5. Y. Higami, S. Wang, H. Takahashi, and K. Saluja, "Adaptive Field Diagnosis for Reducing the Number of Test Patterns," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 412-415, 2017.
  6. Y. Higami, "Fault Simulation using Hazard Signals and Its Application to Fault Diagnosis for Delay Faults," Proc. International Conference for Top and Emerging Computer Scientists, 2017.

2016年度

  1. T. Inamoto, Y. Higami, and S. Kobayashi, "Trip-Based Integer Linear Programming Model for Static Multi-Car Elevator Operation Problems," IEICE Transactions on Fundamentals, Vol. E100-A, No. 2, pp. 385-394, 2017.
  2. T. Inamoto, Y. Higami, and S. Kobayashi, "Road-map to Bridge Theoretical and Practical Approaches for Elevator Operations," Proc. 2016 5th IIAI International Congress on Advanced Applied Informatics, pp. 1097-1102, 2016.
  3. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi, and K. Saluja, "Multi-cycle Test Diagnosis for Path Delay Variations," Proc. Second Taiwan and Japan Conference on Circuits and Systems, 2016.

2015年度

  1. 稲元 勉, "6マルチプレクサ問題における多義性の有用性に関する整数線形計画法に基づく調査," 電気学会論文誌C, Vol. 136, No. 3, pp. 299-307, 2016.
  2. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays," IPSJ Transactions on System LSI Design Methodology, Vol. 9, pp. 13-20, 2016.
  3. T. Inamoto, Y. Higami, and S. Kobayashi, "Giving Formal Roles to Elevators for Breaking Symmetry in Static Elevator Operation Problems," Proc. GCCE-2015 (IEEE 4th Global Conference on Consumer Electronics), pp. 622-625, 2015.
  4. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis for Delay Faults in the Presence of Clock Delays Considering Hazards," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 649-652, 2015.
  5. Y. Higami, S. Wang, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis of Delay Faults Considering Hazards," Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 503-508, 2015.
  6. T. Inamoto, Y. Higami, and S. Kobayashi, "POP-based Approximation Method Enabled by Physical ILP Model for Static Elevator Operation Problems," poster at 22nd International Symposium on Mathematical Optimization (ISMP 2015), 2015.

2014年度

  1. T. Inamoto, Y. Higami, and S. Kobayashi, "Optimal Periods for Probing Convergence of Infinite-stage Dynamic Programmings on GPUs," International Journal of Networking and Computing, Vol. 4, No. 2, pp. 321-335, 2014.
  2. T. Inamoto, Y. Higami, and S. Kobayashi, "Decreasing Computational Times for Solving Static Elevator Operation Problems by Assuming Maximum Waiting Times," Proc. GCCE-2014 (IEEE 3rd Global Conference on Consumer Electronics), pp. 593-596, 2014.
  3. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis of Delay Faults in Multi-Clock SOCs," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 217-220, 2014.
  4. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults," Proc. IEEE Computer Society Annual Symposium on VLSI, pp. 320-326, 2014.
  5. T. Inamoto, Y. Higami, and S. Kobayashi, "A Call-based Integer Programming Model for Static Elevator Operation Problems," Proc. SCIS-ISIS-2014 (The 7th International Conference on Soft Computing and Intelligent Systems & The 15th International Symposium on Advanced Intelligent Systems), pp. 365-369, 2014.

2013年度

  1. T. Inamoto, Y. Higami, and S. Kobayashi, "Injecting Speculation on Ideal Trajectories into a Trip-based Integer Programming Model for Elevator Operations," Proc. GCCE-2013 (IEEE 2nd Global Conference on Consumer Electronics), pp. 23-27, 2013.
  2. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment," IEICE Transactions on Information and Systems, Vol. E96-D, No. 6, pp. 1323-1331, 2013.
  3. T. Inamoto, Y. Higami, and S. Kobayashi, "Intermittently Proving Dynamic Programming to Solve Infinite MDPs on GPUs," Proc. 2013 First International Symposium on Computing and Networking (CANDAR'13) / 5th International Workshop on Parallel and Distributed Algorithms and Applications (PDAA), pp. 252-256, 2013.

2012年度

  1. 稲元 勉, 大野 麻子, 村尾 元, "買い物経路のベクトル化に基づく顧客判別アプローチおよび主成分回帰を用いた適用例," 電気学会論文誌C, Vol. 132, No. 12, pp. 2051-2058, 2012.
  2. S. Yoshinobu, H. Yamaoka, H. Takahashi, Y. Shimizu, and T. Aikyo, "Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool," IEICE Transactions on Information and Systems, Vol. E95-D, No. 4, pp. 1093-1100, 2012.
  3. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis for Bridging Faults on Clock Lines," Proc. Pacific Rim International Symposium on Dependable Computing, pp. 135-144, 2012.
  4. T. Inamoto, C. Ohta, and H. Tamaki, "Gradually Resolving Procedures by a Trip-based Integer Programming to Optimize Elevator Operations," Proc. SCIS-ISIS2012 (The 6th International Conference on Soft Computing and Intelligent Systems & The 13th International Symposium on Advanced Intelligent Systems), pp. 626-632, 2012.
  5. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Diagnosis of Bridging Faults at Gated Clock Lines," Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 2012.

2011年度

  1. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Enhancement of Clock Delay Faults Testing," Proc. European Test Symposium, p. 216, 2011.
  2. T. Inamoto, T. Matsumoto, C. Ohta, H. Tamaki, and H. Murao, "An Implementation of Dynamic Programming for Many-Core Computers," Proc. SICE Annual Conference 2011, pp. 961-966, 2011.
  3. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "On Detecting Transition Faults in the Presence of Clock Delay Faults," Proc. IEEE Twentieth Asian Test Symposium, pp. 1-6, 2011.
  4. Y. Higami, H. Furutani, T. Sakai, S. Kameyama, and H. Takahashi, "Test Pattern Selection for Defect-Aware Test," Proc. IEEE Twentieth Asian Test Symposium, pp. 102-107, 2011.

2010年度

  1. Y. Higami, H. Takahashi, S. Kobayashi, and K. Saluja, "Fault Simulation and Test Generation for Clock Delay Faults," Proc. ASP-DAC, pp. 799-805, 2011.
  2. T. Inamoto, C. Ohta, H. Tamaki, and H. Murao, "An Approach Employing Polysemous Rules to Complement Legacy Rules for the Elevator Operation," Journal of Advanced Mechanical Design, Systems, and Manufacturing (Special issue on Advanced Production Scheduling), Vol. 4, No. 3, pp. 651-663, 2010.

2009年度

  1. Y. Higami, K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, "An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation," IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp. 250-262, 2009.
  2. Y. Higami, K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, "Addressing Defect Coverage through Generating Test Vectors for Transistor Defects," IEICE Transactions on Fundamentals, Vol. E92-A, No. 12, pp. 3506-3513, 2009.
  3. Y. Higami, Y. Kurose, S. Ohno, H. Yamaoka, H. Takahashi, Y. Shimizu, T. Aikyo, and Y. Takamatsu, "Diagnostic Test Generation for Transition Faults Using a Stuck-at ATPG tool," Proc. IEEE Internatioanl Test Conference, pp. 1-9, 2009.
  4. T. Inamoto, H. Tamaki, and H. Murao, "Dynamic Programming on Reduced Models and Its Evaluation through Its Application to Elevator Operation Problems," SICE Journal of Control, Measurement, and System Integration, Vol. 2, No. 4, pp. 213-221, 2009.
  5. 稲元 勉, 太田 能, 玉置 久, 村尾 元, "記号的2値符号化スキームに基づいた動的計画法の代数計算による効率化," 電気学会論文誌C, Vol. 129, No. 7, pp. 1237-1245, 2009.
  6. T. Inamoto, C. Ohta, H. Tamaki, and H. Murao, "An Approach Using Genetics-Based Machine Learning to Complementing Legacy Rules for the Elevator Operation," Proc. International Symposium on Scheduling 2009, pp. 127-132, 2009.

2008年度

  1. 樋上 喜信, 藤尾 昇平, 阿萬 裕久, 高橋 寛, 高松 雄三, "ハードウェアテスト生成ツールを用いた組込みシステムに対するテストケース生成法," 組込みシステムシンポジウム論文集, pp. 151-157, 2008.
  2. Y. Higami, K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, "Maximizing Stuck-open Fault Coverage Using Stuck-at Test Vectors," IEICE Transactions on Fundamentals, Vol. E91-A, No. 12, pp. 3506-3513, 2008.
  3. Y. Higami, K. Saluja, H. Takahasi, S. Kobayashi, and Y. Takamatsu, "Increasing Defect Coverage by Generating Test Vectors for Stuck-open Faults," Proc. IEEE Seventeenth Asian Test Symposium, pp. 97-102, 2008.

2007年度

  1. Y. Higami, K. Saluja, H. Takahasi, S. Kobayashi, and Y. Takamatsu, "Fault Simulation and Test Generation for Transistor Shorts using Stuck-at Test Tools," IEICE Transactions on Information and Systems, Vol. E91-D, No. 3, pp. 690-699, 2008.
  2. 稲元 勉, 玉置 久, 村尾 元, "エレベータ運行計画問題に対する動的計画法の一構成と状態遷移モデルの縮約による効率化," 計測自動制御学会論文誌, Vol. 44, No. 2, pp. 174-182, 2008.
  3. T. Inamoto, H. Tamaki, and H. Murao, "Model-Approximated Dynamic Programming based on Decomposable State Transition Probabilities," Proc. SICE Annual Conference 2007, pp. 2649-2654, 2007.
  4. Y. Higami, K. Saluja, H. Takahasi, S. Kobayashi, and Y. Takamatsu, "Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator," Proc. IEEE Sixteenth Asian Test Symposium, pp. 271-274, 2007.

2006年度

  1. Y. Higami, K. Saluja, H. Takahasi, and Y. Takamatsu, "Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation," Proc. The Twentieth International Conference on VLSI Design, 2007.
  2. Y. Higami, S. Kajihara, I. Pomeranz, S. Kobayashi, and Y. Takamatsu, "On Finding Don’t Cares in Test Sequences for Sequential Circuits," IEICE Transactions on Information and Systems, Vol. E89-D, No. 11, pp. 2748-2755, 2006.
  3. 稲元 勉, 玉置 久, 村尾 元, "遺伝的機械学習によるエレベータ運行ルールの獲得手法," 電気学会論文誌C, Vol. 126, No. 6, pp. 761-770, 2006.
  4. Y. Higami, K. Saluja, H. Takahasi, S. Kobayashi, and Y. Takamatsu, "Diagnosis of Transistor Shorts in Logic Test Environment," Proc. IEEE Fifteenth Asian Test Symposium, pp. 354-359, 2006.
  5. 樋上 喜信, K. Saluja, 高橋 寛, 小林 真也, 高松 雄三, "組合せ回路および順序回路に対する検出・非検出情報に基づく診断用テスト圧縮法," 情報処理学会論文誌, Vol. 47, No. 5, pp. 1269-1277, 2006.

2005年度

  1. Y. Higami, K. Saluja, H. Takahashi, S. Kobayashi, and Y. Takamatsu, "Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits," Proc. The Eleventh Asia and South Pacific Design Automation, 2006.

2004年度

  1. Y. Higami, S. Kajihara, S. Kobayashi, and Y. Takamatsu, "Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Dissipation," Proc. IEEE Thirteenth Asian Test Symposium, 2004.
  2. Y. Higami, M. Sato, H. Takahashi, S. Kobayashi, and Y. Takamatsu, "Acceleration Techniques for Crosstalk Fault Simulation," Proc. International Multi-Conference on ACS-CISIM, 2004.

2003年度

  1. Y. Higami, S. Kobayashi, and Y. Takamatsu, "Generation of Test Sequences with Low Power Dissipation for Sequential Circuits," IEICE Transactions on Information and Systems, Vol. E87-D, No. 3, pp. 530-537, 2004.
  2. 樋上 喜信, 梶原 誠司, 市原 英行, 高松 雄三, "［サーベイ論文］論理回路に対するテストコスト削減法－テストデータ量およびテスト実行時間の削減－," 電子情報通信学会論文誌D-I, Vol. J87-D-I, No. 3, pp. 291-307, 2004.
  3. 稲元 勉, 玉置 久, 村尾 元, 北村 新三, "エレベータ運行計画問題の静的最適化モデルと分枝限定法," 電気学会論文誌C, Vol. 123, No. 7, pp. 1334-1340, 2003.
  4. Y. Higami, S. Kajihara, I. Pomeranz, S. Kobayashi, and Y. Takamatsu, "A Method to Find Don’t Care Values in Test Sequences for Sequential Circuits," Proc. International Conference on Computer Design, pp. 397-399, 2003.

2002年度

  1. Y. Higami, S. Kobayashi, and Y. Takamatsu, "A Method to Reduce Power Dissipation during Test for Sequential Circuits," Proc. IEEE Eleventh Asian Test Symposium, pp. 326-331, 2002.
  2. 樋上 喜信, 小林 真也, 高松 雄三, "順序回路に対する消費電力削減のためのテストベクトル変更法," 情報処理学会論文誌, Vol. 43, No. 5, pp. 1269-1277, 2002.
  3. T. Inamoto, H. Tamaki, H. Murao, and S. Kitamura, "An Application of Branch-and-Bound Method to Deterministic Optimization Model of Elevator Operation Problems," Proc. SICE Annual Conference 2002, pp. 1345-1350, 2002.

2001年度

  1. Y. Higami, S. Kobayashi, and Y. Takamatsu, "Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits," Proc. IEEE International Workshop on Electronic Design, Test and Applications, pp. 431-433, 2002.
  2. Y. Higami, N. Takahashi, and Y. Takamatsu, "Test Generation for Double Stuck-at Faults," Proc. IEEE Asian Test Symposium / IEEE Tenth Asian Test Symposium, pp. 71-75, 2001.
  3. 樋上 喜信, 高松 雄三, 樹下 行三, "リセット機能を持つ順序回路に対するテスト系列圧縮法," 情報処理学会論文誌, Vol. 42, No. 4, pp. 1036-1044, 2001.

2000年度

  1. T. Inamoto, H. Murao, V. Kryssanov, H. Tamaki, and S. Kitamura, "A Study on the Multicriteria Optimization Support by Using Evolutionary Algorithms," Proc. The Sixth International Symposium on Artificial Life and Robotics, Vol. 1, pp. 172-175, 2001.
  2. Y. Higami, K. Saluja, Y. Takamatsu, and K. Kinoshita, "Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits," Journal of Electronic Testing Theory and Applications, Vol. 16, No. 5, pp. 443-452, 2000.
  3. Y. Higami, Y. Takamatsu, and K. Kinoshita, "Test Sequence Compaction for Sequential Circuits with Reset States," Proc. IEEE Asian Test Symposium, pp. 165-170, 2000.

1999年度

  1. T. Inamoto, H. Murao, V. Kryssanov, Y. Kurematsu, and S. Kitamura, "Designing a Pattern Generator for a Walking Robot by Modeling the Human Creative Process," Proc. The Fifth International Symposium on Artificial Life and Robotics, pp. 809-812, 2000.